Matrix-type image display devices (display devices) have come into practical use in office automation equipments and audiovisual equipments, and are used in moving picture display devices having large area and high fineness. Recently, such matrix-type image display devices have been developed as to have, on a single substrate, a display section having pixel arrays, and a peripheral driving circuit section. In such matrix-type image display devices, therefore, a driving circuit is integrated with the display section. Such an arrangement is realized by using polycrystalline silicon as a channel layer of a thin film transistor (TFT). By thus integrating the driving circuit section with the display section on the single substrate, it is possible to lower cost of manufacture and to achieve miniaturization of a module.
With reference to FIG. 7, the following describes a basic arrangement of a liquid crystal display device, which is the matrix-type image display device.
In the liquid crystal display device, vertically and horizontally positioned on a substrate (not shown) are gate lines GL (GL(1), GL(2), . . . GL(X)), which are a plurality of scanning lines (scanning signal lines), and source lines SL (SL(1), SL(2), . . . SL(N)), which are a plurality of data lines (data signal lines). At each intersection of the gate lines GL and the source lines SL, a TFT 30 is provided.
The TFT 30 is connected to one (display electrode) of two electrodes of a pixel capacitor 32 for driving liquid crystal and to one (display electrode) of two electrodes of an auxiliary capacitor 33 for keeping electric charge. The other electrodes of the pixel capacitors 32 and the other electrodes of the auxiliary capacitors 33 are part of a common electrode, which is shared by all the capacitors, and is flatly provided on another substrate arranged face-to-face with the substrate on which the TFT 30 is provided, the liquid crystal being between the two substrates. In other words, the pixel capacitor 32 is formed by compartmentalizing, by the display electrode, the liquid crystal and the common electrode. The pixel capacitor 32 and the TFT 30 connected thereto constitute a display pixel.
In the vicinity of a display section 31 where the TFTs 30 are provided, a source driver (a data signal line driving circuit) 34 and a gate driver (a scanning signal line driving circuit) 35 are provided. Both the source driver 34 and the gate driver 35, as well as the display section 31, are made of polycrystalline silicon, and are integrated onto the single substrate.
The source driver 34 mainly includes a shift register circuit and a plurality of sampling analog switches, which respectively turn ON and OFF in accordance with output signals supplied from output stages of the shift register circuit. The shift register circuit receives, from an external integrated circuit, a clock signal HCK, an inverted clock signal HCKB, which is an inverted signal of the clock signal HCK, and a start pulse HSP. When the start pulse HSP is inputted, the shift register circuit sequentially outputs, from each output stage, the start pulse HSP as a signal having a period being one-half of that of the clock signal HCK or that of the clock signal HCKB. One of two terminals of each sampling analog switch receives, from outside, video data (a video signal) VSIG, while the other of the two terminals of each sampling analog switch is connected to one of the source lines SL. Each of the source lines SL receives the video data VSIG supplied from each output stage of the shift register circuit.
The gate driver 35 mainly includes a shift register circuit. Output stages of the shift register circuit are respectively connected to the gate lines GL. The shift register circuit is receives a clock signal VCK, an inverted clock signal VCKB, which is an inverted signal of the clock signal VCK, and a start pulse VSP. When the start pulse VSP is inputted, the shift register circuit sequentially outputs from each output stage the start pulse VSP as a signal having a period being one-half of that of the clock signal VCK or that of the clock signal VCKB.
To the shift register circuit of the source driver 34 and to the shift register circuit of the gate driver 35, the start pulses HSP and VSP are respectively inputted at the same timing. Each of the source lines SL receives the video data VSIG in accordance with the signals outputted from each output stage of the shift register circuit of the source driver 34. The pixel capacitors 32 and the auxiliary capacitors 33 are respectively supplied with electric charge via the TFTs 30 that are chosen and turned ON in accordance with output signals (a gate signal) from output stages of the shift register circuit of the gate driver 35.
In order to make it possible to freely place such liquid display device, it is necessary to so arrange the liquid display device that a writing position for data to be displayed is symmetrically reversible in upward and downward directions or in rightward and leftward directions. For example, by so arranging the liquid display device that it is possible to switch shifting directions of the shift register circuit in the source driver 34 between the rightward direction and the leftward direction, it is possible to freely inverted displayed images in the rightward and leftward directions.
Therefore, there has been a practice of adopting an arrangement in which the source driver includes a shift register circuit that is capable of switching shifting directions between two directions. Moreover, because in many cases a matrix-type image display device has an even number of source lines SL, an arrangement is necessary in which it is possible to switch the shifting directions even if the matrix-type image display device has an even number of source lines SL.
FIG. 8 shows a circuit arrangement of a conventional source driver including the shift register circuit that is capable of switching shifting directions between two directions. The circuit arrangement is described in Japanese Publication for Unexamined Patent Application, Tokukai, No. 2001-228830 (publication date: Aug. 24, 2001), for example.
In this circuit arrangement, a shift register circuit 51 is unit circuits (not shown) connected in cascade connection. Each of the unit circuits includes four clocked inverters. It is so arranged that each of the unit circuits receives a shifting directions switching signal and an inverted shifting directions switching signal LR (not shown) as well as the clock signal HCK and the inverted clock signal HCKB.
Output stages of the shift register circuit 51 (SR in FIG. 8) are respectively connected to sampling analog switches 53. One of two terminals of each sampling analog switch 53 is connected to a video data line 54, and the others of the two terminals of the sampling analog switches 53 are respectively connected to the source lines SL. The sampling analog switches 53 operate in accordance with respective output signals supplied from output stages of the shift register circuit 51 and control writing of the video data VSIG into the respective source lines SL. In order to limit pulse width of the output signal outputted from each output stage, the shift register circuit 51 may include an arrangement in which the output signal from each output stage and an external signal (for example, the clock signal HCK or the inverted clock signal HCKB) are ANDed.
Here, the shift register circuit 51 has an even number of output stages because the number of output stages are so arranged as to be equal to the number of the source lines SL. However, when the shift register circuit 51 has an even number of output stages, because the clock signal supplied to the leftmost output stage and the clock signal supplied to the rightmost output stage are different (the clock signal HCK is supplied to the leftmost stage, and the inverted clock signal HCKB is supplied to the rightmost stage), shifting timings of the clock signals and the video data VSIG are shifted by half a period when the shifting directions are switched from the rightward direction to the leftward direction, or vice versa. Thus, in order to eliminate such shifting of timings, clock lines 55 have switching circuits 52 for reversing, in switching the shifting directions, polarities of the clock signal HCK and the inverted clock signal HCKB.
With such circuit arrangement, even if there are an even number of the source lines SL, it is possible to switch the shifting directions between the rightward and leftward directions by reversing, in switching the shifting directions, the polarities of the clock signal HCK and the inverted clock signal HCKB by using the switching circuits 52.
FIG. 9 shows a circuit arrangement of another conventional source driver including the shift register circuit that is capable of switching shifting directions between two directions.
According to the circuit arrangement shown in FIG. 9, a shift register circuit 61 has output stages, the number of which is larger than that of the source lines SL by three. A total of three dummy pixel columns 62 for adjustment are provided so as to sandwich effective pixel columns 63 to be driven by the source lines SL. The outmost two dummy pixel columns are always dummy, and do not contribute to displaying. On the other hand, a second pixel column from the right and a second pixel column from the left in FIG. 9 respectively become a dummy pixel column and an effective pixel column, or an effective pixel column and a dummy pixel column, in accordance with the shifting directions. FIG. 9 illustrates a case in which the second pixel column from the right is the dummy pixel column 62, and the second pixel column from the left is the effective pixel column 63.
FIG. 10 shows a circuit arrangement of yet another conventional source driver including the shift register circuit that is capable of switching shifting directions between two directions. An arrangement equivalent to the circuit arrangement is described, for example, in Japanese Publication for Unexamined Patent Application, Tokukaihei, No. 11-272226 (publication date: Oct. 8, 1999).
According to the circuit arrangement shown in FIG. 10, a shift register circuit 71 has output stages, the number of which is larger than that of the source lines SL by one, so that the number of the output stages becomes an odd number. Output stages of the shift register circuit 71 are provided with NAND circuits 72, to which output signals supplied from two adjacent output stages are inputted for NAND operation.
However, the circuit arrangements in FIGS. 8 to 10 have the following problems.
According to the circuit arrangement in FIG. 8, the polarities of the clock signal HCK and the inverted clock signal HCKB are switched when the shifting directions are switched, by providing the switching circuits 52 to the clock lines 55. This causes a problem in dealing with a high clock frequency. In order to respond to the heightened frequency, it is preferable that the circuit arrangement is such that it is possible to directly use the clock signal HCK, the inverted clock signal HCKB, and the start pulse HSP, which are external signals.
On the other hand, according to the circuit arrangements in FIGS. 9 and 10, the shift register circuits 61 and 71 have an odd number of stages, and the clock signal HCK is supplied to the leftmost output stage and the rightmost output stage. Because of this, it is not necessary to switch the polarities of the clock signal HCK and the inverted clock signal HCKB in switching the shifting directions. Therefore, there is no problem in dealing with a high clock frequency.
However, according to the circuit arrangement in FIG. 9, the number of the output stages of the shift register circuit 61 is set to be an odd number, and the second pixel column from the right and the second pixel column from the left are respectively arranged to be the dummy pixel column 62 and the effective pixel column 63, or the effective pixel column 63 and the dummy pixel column 62, in accordance with the shifting directions. This causes a problem that an image displaying position within an image module is shifted by one column.
On the other hand, according to the circuit arrangement in FIG. 10, the shift register circuit 71 has an odd number of output stages. By performing NAND operation, however, the number of output signals supplied from each of the NAND circuits 72 becomes an even number. Because of this, it is possible to obtain equivalent signals in the rightward shifting and the leftward shifting, thereby causing no such problem as in the circuit arrangement in FIG. 9 in which the image is shifted.
According to the circuit arrangement in FIG. 10, it is not necessary to convert external input signals, such as the clock signal HCK and the inverted clock signal HCKB, inputted to the shift register circuit 71. However, because it is so arranged that the output signals supplied from two adjacent output stages in the shift register circuit 71 are NANDed, the output signals supplied from the two adjacent output stages must be outputted in such timing as to overlap with each other. The arrangement of the shift register circuit 71 is thus limited.
On the other hand, the shift register circuit 51 in FIG. 8 and the shift register circuit 61 in FIG. 9 may be so arranged that the output signals supplied from two adjacent output stages are outputted in such timing as to overlap with each other, or in such timing as not to overlap with each other.
Moreover, according to an arrangement in which the output signals supplied from two adjacent output stages are outputted in such timing as to overlap with each other, a HIGH period becomes longer when compared to an arrangement in which the output signals are not overlapped. This results in more electric power consumption if it is so arranged that current is supplied during the HIGH period.